1. Field of the Invention
The present invention relates in general to a semiconductor package, and more particularly to a resin molded semiconductor package of which a predetermined volume is hermetically sealed by a mold resin to form a package body.
2. Background of the Prior Art
With reference to FIGS. 1 and 2, there are shown a small outline J-lead package and a small outline package in accordance with the prior art, respectively. Each of the semiconductor packages of the prior art comprises a semiconductor chip 1 having a predetermined shape and mounted on a paddle 2 of a lead frame. The lead frame further comprises a plurality of inner leads 3, connected to the semiconductor chip 1 through a plurality of metal wires 5 which will be described later herein, and a plurality of outer leads 4 outwardly extending from individual inner leads 3. The semiconductor chip 1 is electrically connected to the inner leads 3 of the lead frame through the plurality of metal wires 5. In the known package, a predetermined volume including the semiconductor chip 1 and the inner leads 3 electrically connected to the chip 1 is packaged or hermetically sealed by a mold resin 6 to form a package body.
In the drawings, the reference numeral 7 denotes chip bonding material for bonding the semiconductor chip 1 to the surface of the paddle 2 of the lead frame.
FIG. 3 shows in a plan view a structure of a conventional lead frame of the semiconductor package. As shown in this drawing, the paddle 2 of the lead frame is supported by a pair of connection bars 9 and 9' which connect the opposite ends of the paddle 2 to an opposed pair of side rails 8 and 8', respectively. The plurality of inner leads 3 and the plurality of outer leads 4 are integrally formed with each other and arranged on opposite sides of the paddle 2. Each of the leads, comprising an inner lead 3 and an outer lead 4, is connected to the other leads and supported by dambars 10.
In order to assembly the semiconductor package having the construction described above, the semiconductor chip 1 which is provided by sawing the wafer is first bonded to the surface of the paddle 2 of the lead frame using the chip bonding material 7. The lead frame having the semiconductor chip 1 bonded to the surface of the paddle 2 is, thereafter, subjected to a high temperature curing so as to cure the bonding material 7.
Thereafter, a wire bonding step is carried out to electrically connect the inner leads 3 of the lead frame to individual bond pads of the semiconductor chip 1 using the metal wires 5, such as gold wires or aluminum wires.
Upon finishing the wire bonding step, the predetermined volume including the semiconductor chip 1 and the inner leads 3 of the lead frame is hermetically sealed by the mold resin 6 to form the package body. Thereafter, the remnant of the mold resin 6 is removed from the package body prior to plating of the outer leads 4 of the lead frame using tin and lead.
After the plating of the outer leads 4, a trimming step and a forming step are carried out in series. In the trimming step, the dambars 10 connecting the leads to each other and the connection bars 9 and 9' connecting the paddle 2 to the side rails 8 and 8' are cut off to separate the packages from each other. In the forming step, the outer leads 4 of the lead frame protruding out of the package body are bent to a predetermined bent shape, thereby preparing a desired semiconductor package such as shown in FIG. 1 or 2. The known semiconductor packages are conventionally classified into several types in accordance with the bent shape of the outer leads 4 of the lead frame. Otherwise stated, the known semiconductor packages are generally classified into a small outline J-lead package such as shown in FIG. 1, a small outline package (SOP) package such as shown in FIG. 2 and a dual inline package (not shown).
The semiconductor packages prepared by the process described above should be subjected to an electric performance test prior to practical use. In practical use, the semiconductor package is mounted on a printed circuit board (not shown) by a surface mounting technique or an insert mounting technique and gives its predetermined function to an electronic equipment provided with it.
However, each of the known semiconductor packages requires a substantial mounting area on the printed circuit board due to its outer leads protruding out of the package body while there is some difference in the mounting area in accordance with the types of the semiconductor packages. Thus, each of the known semiconductor packages has a problem that it causes deterioration of space efficiency of the printed circuit board and this results in deterioration of package mounting efficiency. Another problem of the known semiconductor packages is that the outer leads are apt to be undesirably bent when the packages are mounted on the printed circuit board or transported, thereby causing quality inferiority.
In addition, since the metal paddle of the lead frame is different in the thermal expansion coefficient from the semiconductor chip, so that the known semiconductor package is easily broken during its mounting on the printed circuit board and there easily occurs separation of the interface between the semiconductor chip and the metal paddle. Furthermore, the preparation process of the known semiconductor package comprises several complex steps and this causes increase of manufacturing cost of the packages as well as installation cost of the package manufacturing equipment. The outer leads protruding out of the package body may result in deterioration of lead contact during the electric performance test, thus deteriorating limit of error of the testing.